Design how should be oneself finished with processor only?

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Since such, can discuss how to finish this job with you I am very glad. Delivery other people we speak of from the result first, namely the final delivery other people of this task. Might as well here the Deliverables of referenced ARM processor nucleus. Of course, if be a special processor that oneself use only, must not have so whole pay thing. Hardware: ?  of Tao  Qian whetstones provide dinner for code of TL of Mo of rostellum an ancient nationality in China, environment of test and verify, the script of EDA tool, documentation is waited a moment. Tool: ? ?compiler) of ぞ of wooden tablets or slips for writing of Qi of ū of Tao   , debugging aids (Debugger) , emulation tool (Simulator) and function analysis tool (Profiler) . Next graphs are the compiles a tool example of ARM, basically include Armclang(C to compile implement) , armasm(assembler) , armlink(is linked implement) with Fromelf(image tool) . Emulation tool includes Instruction Set Simulator (ISS) of an instruction emulator at least commonly, those who do have Cycle-accurate ISS well. Model: ? The model that sends the processor IP with general now? to still can offer a few processor will support systematic level design, use at fictitious platform for instance (the processor Model of Virtual Platform. Fictitious platform can be below the circumstance that does not have hardware supportive software development, it is OK imitate a complete chip or a hardware board gets stuck, for instance the Fixed Virtual Platform (FVP) of ARM. And appropriative processor model (the main component that for instance the Fast Model) of ARM is fictitious platform, with bus line model and other IP model the function of an imitate system. In afore-mentioned delivery other people, red is indispensable content. Although you are done special processor function is simple, without this a few parts it also cannot be used normally almost. Of course, you can say, I do not need ISS to do instruction test and verify, do not need Debugger to do debug, do not need C to compile implement and use collection only, I also can " breathe out ah " . See this one pile works, if you are done not have cowardly, feel very interesting however. So I also am willing to nod a help to you very much, look to be able to turn your think of a way into reality. The method is very actually simple also, oneself cannot be done search " others " help. Specific for, according to your budgetary situation, can divide for " poor " and " rich " two kinds play a way. I say those who have money to play a way first. Rich play a way actually, more than your person wants to become special processor, very much big company also has such demand. So, provide understanding technically for this kind of demand with respect to somebody definitely plan, for instance the Xtensa of the ASIP-designer tool of Synopsys and Cadence can expand processor (refer to Cadence(Tensilica) but custom-built processor) , it is to satisfy the requirement of custom-built processor and of the design. Among them of Cadence can expand processor is configuration was offerred to you on processor of a foundation (Configure) and patulous (the method of Extension) and tool. The function that it provides can be experienced through laying a plan. The input of this tool includes 3 shares: 1) pattern plate of a processor (Processor Template);2) user is configured (the instruction with custom-built Configuratoin Options);3) (Custom Instructions) . The simplest case, it is OK that you should choose pattern plate of a processor to throw a tool only. If this cannot satisfy a requirement, so you should do a few configuration possibly. This is very simple also, basic it is menu choice. What have technical content most is the 3rd kind of circumstance, you should design a few custom-built statements. Had these inputs, the issue that remain gives tool. Those pay thing that we say in the first, can generate automatically. So how do we know otherwise wants him custom-built instruction? The tool also provided a means. Above all, input your algorithmic order input, the course is compiled, undertake emulation mixing Profiling, the result that gets function is evaluated. Judge whether contented demand next. The answer is the word of NO, if still be no good,update Configuration; with respect to the attempt, try the method of custom-built instruction again, till satisfaction till. Because the tool helped you do major work, the process of this iteration (also can be being regarded is Design Space Exploration) the meeting is very quick. To implement custom-built directive (undertake patulous) to original statement collect, cadence(Tensilica) designed a kind of appropriative to describe a language: TEnsilica Instruction Extension (TIE) Language. Because Xtensa processor has a basic framework pattern plate, use TIE language undertakes expanding to it is to have certain restriction, not be to say you think the statement that make and framework alter can come true. The tool that Synopsys provides calls ASIP Designer directly, ASIP(Application-Specific Processor) designs a tool with processor only. With Tensilica can expand processor differs, ASIP Designer supports from 0 begin to design and realize a special processor. Corresponding, it can expand than Tensilica processor has taller flexibility. You are OK the design instruction collect of unusual freedom and small structure, enclothe from Extensible Processor, to Application-specific UP/DSP, to Programmable Datapath a such larger framework spaces, following plan institute are shown. Here also can see, the target of this tool is not to design universal processor. The graph is the methodology with this complete tool. Its input is two, algorithmic (C/C++ code) with processor model (Processor Model) , output is all designs related a processor and tool catenary. Arrive from the input likewise automation completes the process of output. Of course, this process does not resemble looking so simple, the doorsill that processor builds a model is not low. And, the tool gifts your flexibility is taller, the threshold that masters this kind of tool is higher also. The processor of ASIP Designer builds a model to need to use a kind of special language, namely NML, undertake to the instruction collect of processor and framework high administrative levels builds modular; to still need in addition a lot of and compile implement relevant design, (Everybody can visit material information Synopsys website) . So, although you can be canned afford, want to had played this to cover a tool, must still have two conditions: ? Show off? is you must be familiar with processor framework and compile respect knowledge; the 2nd, it is to should learn this to cover the language that build a model and tool. As a whole, if you have the demand that designs with processor only, the patience of sufficient financing and study, can consider to introduce tool of this kind of subdesign. After the study with too certain experience is periodic, you can complete a design not only, return the capability that can obtain processor of fast, efficient design. Played a law to see the introduction above thoroughly, you also are opposite " automatic " the method that devises special processor very be envious? Regrettablly, you may buy such tool without sufficient financing, or your target accrual is undeserved still make such investment. Below this kind of circumstance, I suggest you from the processor that opens a source (perhaps dictate collect) the special processor that begins to do yourself. Actually this also is gibberish. Still get a particular case so, assume you want to custom-built processor is become on the foundation in RSIC-V. RSIC-V is the processor opening a source of an opposite maturity dictates now, had had a lot of relevant implementation and very active community. Believe everybody has heard of, not popular science. Here must explain, I had not had thorough research and attempt to RISC-V, the following view basically is be an armchair strategist, wrong place asks everybody to criticize point out mistakes so that they can be corrected. Above all, you want to learn RISC-V to dictate collect manual is medium well " Chapter 10 Extending RISC-V " , here introduced clearly to dictate to RISC-V collect increases the regulation of the instruction. The 2nd, the foundation comes true to go up in the hardware of existing RISC-V, increase the hardware of new statement correspondence. The likelihood needs to increase appropriative register, operation unit, pipeline register, control signal is waited a moment. Or, you are OK according to new instruction market (cry suppose " RISC-V++ ISA " ) oneself do complete hardware to come true. Actually I feel the 2nd kind of method is returned more rely on chart a bit. A lot of moment, the thing of modification others, what should do difficulty than oneself is much. The 3rd, in the tool chain with original RISC-V (for instance GNU or of LLVM compile implement) make on the foundation revise, support new statement. Opposite for, this job has more perfect regulation, want to be able to dictate what add newly according to the regulation that compiles a tool only add. Of course, if you increase the statement is more special, it is vector operation for instance, so the design of tool catenary will be a lot of more difficult. A choice below this kind of circumstance is in advanced course language compile implement in the support that does not increase pair of new statements, these new statements with collection or the method of Intrinsic comes true. Finally, can this method also support in the 2nd fast Design Space Exploration that says in the section? Main train of thought also is about the same. The algorithmic; basis that you can emulate you first with basic instruction collect the result of Profiling (for instance function index, instruction efficiency, code Size) the modification; that the consideration undertakes to instruction collect updates corresponding hardware implementation and tool catenary next, be compiled again and emulate your algorithm, do not break iteration. You realize what this process provides without automatic chemical industry to help now, the likelihood needs longer time ability to finish, need to wait for Implementation result to have optimized case to power comsumption area especially. Of course, if there had been subdesign tool in the zoology of RSIC-V now, so likely the circumstance will be a few more relaxed. This kind of method goes it seems that, the hole among is very much nevertheless, ask you are right fundamental processor (RISC-V) is very for instance familiar. Suit those already complete players that had become RISC-V implementation to try. Otherwise, perhaps some hole you are impassable at all. Finally, I write this article is not to want to encourage everybody oneself become special processor, hope everybody is clear about the cost that makes this thing want to pay however. CNC Milling